The present invention relates generally to a semiconductor device and a method operating the same, and more specifically, to a technology related to a nonvolatile memory device for sensing data using resistance change.
Generally, memory devices may be classified as a volatile memory device or a nonvolatile memory device. A nonvolatile memory device includes a nonvolatile memory cell capable of preserving stored data even when a power source is off. For example, a nonvolatile memory device may be implemented as a flash random access memory (RAM) device, a phase change RAM (PCRAM) device, or the like.
A PCRAM device includes memory cells that are implemented using a phase change material, for example, germanium antimony tellurium (GST), and is configured to store data in the memory cells by applying heat to the GST so that the GST changes into a crystal or amorphous phase.
A nonvolatile memory device, such as a magnetic memory device, a phase change memory (PCM) device, or the like, has a data processing speed similar to that of a volatile RAM device. A nonvolatile memory device also preserves data even when a power source is off.
FIGS. 1a and 1b illustrates a conventional phase change resistance device 4.
Referring to FIGS. 1a and 1b, the phase change resistance device 4 includes an upper electrode 1, a lower electrode 3, and a phase change material 2 interposed between the upper electrode 1 and the lower electrode 3. When a voltage is applied to the upper electrode 1 and the lower electrode 3, a current flows into the phase change material 2, and thus a high temperature is induced in the phase change material 2. The electrical conductive state of the phase change material 2 changes depending on resistance variation due to the high temperature.
FIGS. 2a and 2b illustrates a data storage principle of the conventional phase change resistance device 4.
Referring to FIG. 2a, when a current below a critical value flows into the phase change resistance device 4, the phase change material 2 is crystallized. When the phase change material 2 changes into a crystal phase, it becomes a low resistance material. As a result, a current can flow between the upper electrode 1 and the lower electrode 3.
On the other hand, referring to FIG. 2b, when a current over the critical value flows into the phase change resistance device 4, the temperature of the phase change material 2 increases to over a melting point. When the phase change material 2 melts into an amorphous phase, it becomes a high resistance material. As a result, a current cannot easily flow between the upper electrode 1 and the lower electrode 3.
As described above, the phase change resistance device 4 can store data corresponding to two resistance phases. For example, in the phase change resistance device 4, the low resistance phase may correspond to data “1” and the high resistance phase may correspond to data “0.”
Also, this data can be stored in the phase change resistance device 4 as nonvolatile data because the status of the phase change resistance material 2 does not change even when a power source is off.
FIG. 3 illustrates a write operation of a conventional phase change resistance cell.
Referring to FIG. 3, heat is generated if a current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance device 4 for a given time.
When a current below the critical value flows for a given time, the phase change material 2 changes into a crystalline phase formed by a low temperature heating status. As a result, the phase change resistance device 4 becomes a low resistance element with a set phase.
On the other hand, when a current over the critical value flows for a given time, the phase change material 2 changes into an amorphous phase formed by a high temperature heating status. As a result, the phase change resistance device 4 becomes a high resistance element having with a reset phase.
By using the properties described above, a low voltage may be applied to the phase change resistance device 4 for a long time in order to write the set phase in the write operation.
On the other hand, a high voltage may be applied to the phase change resistance device 4 for a short time in order to write the reset phase in the write operation.
In a sensing operation, a phase change resistance memory applies a sensing current to the phase change resistance device 4 to sense data written in the phase change resistance device 4.
Meanwhile, this nonvolatile memory device performs a verification read operation for judging whether a desired resistance is obtained so as to determine whether a program operation is continuously performed or not.
However, when the program operation and the verification read operation are accurately performed in an actual test operation, it is difficult to determine whether there is a problem in the verification read operation or the program operation. If it is possible to figure out a verification read value, it is easy to determine the cause of the problem.
FIG. 4 illustrates an operational timing diagram of a read operation in a conventional nonvolatile memory device.
Generally, a program and verify read (PNV) operation includes a verification read operation that is performed before performing a program operation so as to compare data written in a current cell with data to be written in the current cell.
If the data written in the current cell is identical to the data to be written, a program flag signal is disabled indicating to a program state machine (PSM) not perform the program operation.
On the other hand, if the data written in the current cell is different from the data to be written, the program flag signal is enabled. The enabled program flag signal is sent to the PSM to perform the program operation.
Each of output data S/A<0>˜S/A<X> sensed by a sense amplifier is outputted to a read global input/output line RGIO. In a normal read operation, when latch enable signals LEN<0>˜LEN<X> are sequentially enabled, read data is sequentially latched in data latches D_Lat<0>˜D_Lat<X>.
However, in this conventional nonvolatile memory device, the output data S/A<0>˜S/A<X> are sequentially stored in the data latches D_Lat<0>˜D_Lat<X> but it is difficult to find out a data value read in the verification read operation.
When defects are generated in actual program and verification read operations, it is impossible to determine whether a cause of the defects results from the program operation or the verification operation. Moreover, it is difficult to distinguish the normal read operation from the verification read operation.